The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain electrodes between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes.
The complexity of ICs and the number of devices incorporated in ICs are continually increasing. As the number of devices in an IC increases, the size of individual devices decreases. Device size in an IC is usually noted by the minimum feature size; that is, the minimum line width or the minimum spacing that is allowed by the circuit design rules. As the semiconductor industry moves to a minimum feature size of 45 nanometers (nm) and even smaller, the gain of performance due to scaling becomes limited. As new generations of integrated circuits and the transistors that are used to implement those ICs are designed, technologists must rely heavily on non-conventional elements to boost device performance
The performance of a MOS transistor, as measured by its current carrying capability, is proportional to the mobility of a majority carrier in the transistor channel. By applying an appropriate longitudinal stress to the transistor channel of a MOS transistor the mobility of the majority carrier in the transistor channel can be increased. For example, applying a compressive longitudinal stress to the channel of a P-channel MOS (PMOS) transistor enhances the mobility of majority carrier holes. Similarly, applying a tensile longitudinal stress to the channel of an N-channel MOS (NMOS) transistor enhances the mobility of majority carrier electrons. The known stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance.
In P-channel MOS (PMOS) transistors a longitudinal compressive stress can be created by embedding silicon germanium (eSiGe) adjacent the transistor channel to enhance the mobility of holes. To fabricate such a device a trench or recess is etched into a silicon substrate to create trenches in the silicon substrate. The trenches can then be filled using selective epitaxial growth of silicon germanium to produce embedded silicon-germanium (or “eSiGe”) regions. The eSiGe regions can then eventually be used to create source/drain (S/D) areas or regions of a MOSFET device. The silicon substrate and the SiGe regions grown by the selective epitaxial process have a crystal lattice mismatch which causes intrinsic mechanical stresses in the PMOS transistor. These intrinsic mechanical stresses increase the hole mobility in the silicon channel of the PMOS transistor which can improve drive current which in turn improves performance of the PMOS transistor.
A number of difficulties are encountered in the selective epitaxial growth process needed to implement eSiGe. These include formation of epitaxial crystal defects which cause device failures, non-uniform SiGe thickness that causes variations in device parameters, intrinsic stress relaxation in SiGe that reduces device performance, high cost of the selective epitaxial processes, and complexity of integration of the selective epitaxial growth of such eSiGe regions into CMOS fabrication process.
The thickness of the eSiGe film determines the stress/stain that can be applied to the channel of the MOSFET device. As such, performance enhancements which can be realized from an embedded process are proportional to the thickness of the embedded SiGe grown in the trenches. When thinner silicon layers are used, the potential depth of trenches which can be formed in the substrate is reduced, and hence the potential thickness of the eSiGe regions is also reduced. As such, the thickness of the eSiGe that can be realized is insufficient to achieve a desired channel stress and mobility gain. For example, in conventional eSiGe processes on silicon-on-insulator (SOI), transistors are fabricated in a thin silicon layer that has a thickness between 50 nanometers (nm) to 100 nm, and the thickness of trenches which can be etched and then filled with SiGe is limited to between 40 and 60 nm. When the thickness of the eSiGe layer is limited to thicknesses within this range, the eSiGe source/drain areas are not capable of generating appropriate or suitable channel strain/stress. Moreover, when ultra-thin silicon-on-insulator (UTSOI) substrates are employed which have a silicon substrate having a thickness of 10 nm or less, it is difficult if not impossible to form trenches or recesses in the silicon substrate so that eSiGe techniques can be utilized.
In an epitaxial growth process a growing material layer substantially mimics the lattice structure of a surface upon which it is growing. Any contamination or damage of the substrate surface causes formation of the growth-in defects in epitaxial layers. The sidewalls of the trenches in silicon substrates are prone to such contamination and/or damage due to reactive ion etching (RIE) processes used. As a result, selective epitaxial regions of eSiGe often have crystal defects at the sidewalls. These defects cause stress relaxation in eSiGe and variations in device parameters.
Accordingly, it is desirable to optimize methods for fabricating stress enhanced MOS transistors. In addition, it is desirable to provide an optimized stress enhanced MOS transistor that avoids the problems attendant with conventional transistor fabrication. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.